A frequency synthesizer to which PLL (Phase Locked Loop) is applied as one of standard signal generators is known. As shown in FIG. 12, in the frequency synthesizer, a voltage-controlled oscillator 201 is subjected to 1/N frequency division by a frequency divider 202 and the frequency-division output is input to one input terminal of a phase comparator 203. In addition, an oscillation output of a crystal oscillator 204 as a reference signal generator is subjected to 1/M frequency-division by a frequency divider 200 and the frequency-division output is input to the other input terminal of the phase comparator 203. The comparison signal therebetween is fed back to the voltage-controlled oscillator 201 through a loop filter 205, thereby constructing PLL (for example, Patent Document 1). When PLL is locked, the frequency fvco of the oscillation output of the voltage-controlled oscillator 201 and the frequency f0 of the oscillation output of the crystal oscillator 204 satisfy the following relationship: fvco/N=f0/M, and thus fvco=(N/M)f0. The frequency divider 202 is constructed by a programmable counter, and the frequency division ratio N can be set on the basis of digital data from the external, so that the frequency of fvco can be freely set.
For example, the frequency synthesizer is applied as a station oscillating unit at a mobile station. That is, at a base station, a predetermined frequency band is allocated to a mobile station. Therefore, it is necessary for the mobile station side to generate an oscillation output of the allocated frequency band, and thus it is required to bring the station oscillating unit with a function of adjusting the frequency. Furthermore, the frequency synthesizer is also used for a test signal source of radio communication equipment, broadcasting equipment or the like.
As described above, for example when the frequency synthesizer is applied in a communication field, it is required that noise is little to avoid cross talk with other channels. Furthermore, since electric waves are congested, it is desired that the frequency can be set as finely as possible. In order to set the frequency finely, the frequency division ratio N described above may be increased. However, if the frequency division ratio is excessively increased, noise becomes large due to elongation of a delay occurring in a loop, and actually the upper limit of N is equal to about 1000.
Therefore, for convenience of description, for example when a frequency synthesizer in which the frequency of about 1000 MHz can be adjusted every 1 Hz is designed, the apparatus of FIG. 12 must be designed in a multistage style. That is, when the upper limit of N is equal to 1000, by setting the frequency (M/f0) of a reference signal input to the phase comparator to 1 MHz, a frequency synthesizer of 1 MHz to 1000 MHz in which the frequency can be set every 1 MHz can be manufactured. Likewise, by setting the frequency of the reference signal to 1 kHz, a frequency synthesizer of 1 kHz to 1 MHz in which the frequency can be set every 1 kHz can be manufactured. Likewise, by setting the frequency of the reference signal to 1 Hz, a frequency synthesizer of 1 Hz to 1 kHz in which the frequency can be set every 1 Hz can be manufactured. By stepwise combining the respective frequency synthesizers, a frequency synthesizer in which the frequency can be set every 1 Hz until 1000 MHz can be obtained.
However, in this case, PLL must be constructed with respect to each synthesizing circuit for synthesizing frequencies, and thus there is a problem that the circuit construction is complicated, the number of parts is increased and noise is increased.
Therefore, the inventor of this application has developed a novel type frequency synthesizer which can finely set the frequency over a broad band by adopting a novel construction which is completely different from the conventional frequency synthesizers on principle, however, has run into trouble in that the frequency entraining range is narrow and the frequency entrainment cannot be surely performed in consideration of the dispersion of products of the voltage-controlled oscillation unit, the temperature characteristic, etc. Accordingly, the above problems must be overcome to put the frequency synthesizer concerned to practical use. Furthermore, this frequency synthesizer comprises analog circuits and digital circuits, and has a problem that noise caused by simultaneous switching of many switching elements in a digital/analog converter must be suppressed.
Patent Document 1
JP-A-2004-274673